We are looking for an experienced Senior Staff Design Verification Engineer to join our dynamic team in Austin, TX. The ideal candidate will have experience in semiconductor design verification and a proven track record of success in developing and executing verification plans for complex SoC designs.
What's in it for the candidate
- You will join a dynamic team and work on AI edge designs for Internet of Things (IoT) applications.
- We are a rapidly growing company with a great work culture.
Responsibilities
You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.
Specific responsibilities include:
- The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
- Develop test plans at block, sub-system, and chip level.
- Execute SoC-based verification at full-chip.
- Write C-based lib packages and tests.
- Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
- Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
- Automating the test environment for randomized testing and scoreboarding.
- Utilize advanced debugging techniques to identify and resolve design and verification issues.
- Perform root-cause analysis and work with design teams to fix identified issues
- Define and track functional and code coverage metrics to ensure thorough verification.
- Ensure that verification quality meets or exceeds industry standards and project requirements.
- Edge-based AI inference is preferred.
Required Skills / Qualifications:
Bachelor Degree in Electrical or Computer Engineering
Minimum 6 years of design verification experience for complex SoC designs
Preferred Skills / Qualifications:
-experience in block, subsystem and full-chip verification
- Should have delivered multiple chips functioning to Specification.
- Identify and manage verification deliverables, milestones, and schedules.
- Proactively identify potential verification risks and develop mitigation strategies.
- Collaborate with design, architecture, and software teams to understand and verify design intent.
- Communicate verification progress, issues, and results to stakeholders and management.
- Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges
- Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
- C-based verification in an SoC environment is required
- Experience with ARM processor-based designs and low-power design techniques is a plus.
- Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile
- Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5
- Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power
Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are an Equal Opportunity Employer. Race/Color/Gender/Religion/National Origin/Disability/Veteran.
Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.
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Aleron
Jul 28, 2025